Semiconductor memory device

ABSTRACT

A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation application based on pending application Ser. No.15/653,198, filed Jul. 18, 2017, the entire contents of which is herebyincorporated by reference.

Korean Patent Application No. 10-2016-0163757, filed on Dec. 2, 2016, inthe Korean Intellectual Property Office, and entitled: “SemiconductorMemory Device and Method of Manufacturing the Same,” is incorporated byreference herein in its entirety.

BACKGROUND 1. Field

Embodiments relate to a semiconductor memory device and a method ofmanufacturing the same.

2. Description of the Related Art

Semiconductor devices are widely used in an electronic industry becauseof their small sizes, multi-functional characteristics, and/or lowmanufacture costs. Semiconductor devices have been highly integratedwith the development of the electronic industry. Widths of patternsincluded in semiconductor devices have been reduced to help increase theintegration density of semiconductor devices.

SUMMARY

The embodiments may be realized by providing a method of manufacturing asemiconductor memory device, the method including providing a substratethat includes a cell array region and a peripheral circuit region;forming a mask pattern that covers the cell array region and exposes theperipheral circuit region; growing a semiconductor layer on theperipheral circuit region exposed by the mask pattern such that thesemiconductor layer has a different lattice constant from the substrate;forming a buffer layer that covers the cell array region and exposes thesemiconductor layer; forming a conductive layer that covers the bufferlayer and the semiconductor layer; and patterning the conductive layerto form conductive lines on the cell array region and to form a gateelectrode on the peripheral circuit region.

The embodiments may be realized by providing a semiconductor memorydevice including a substrate that includes active regions defined by adevice isolation layer; word line structures filling trenches formed inan upper portion of the substrate, the word line structures intersectingthe active regions to divide the active regions into first dopantregions and second dopant regions; bit lines intersecting the word linestructures, the bit lines being connected to the first dopant regions;and data storage parts connected to the second dopant regions, whereineach of the word line structures includes a word line, a cappingpattern, and a remaining pattern, which are sequentially stacked in eachof the trenches.

The embodiments may be realized by providing a method of manufacturing asemiconductor memory device, the method including providing a substratesuch that the substrate includes a cell array region and a peripheralcircuit region such that the substrate includes a trench in the cellarray region; forming a capping pattern in the trench such that thecapping pattern extends to an opening of the trench; removing a portionof the capping pattern at the opening of the trench such that a recessregion is formed at the opening of the trench; forming a mask patternthat covers the cell array region and exposes the peripheral circuitregion such that the mask pattern is in the recess region at the openingof the trench; growing a semiconductor layer on the peripheral circuitregion such that the semiconductor layer has a different latticeconstant from the substrate; removing portions of the mask pattern suchthat a remaining pattern of the mask pattern remains in the trenchadjacent to the opening of the trench; forming a buffer layer thatcovers the cell array region and exposes the semiconductor layer;forming conductive lines on the cell array region and a gate electrodeon the peripheral circuit region.

BRIEF DESCRIPTION OF THE DRAWINGS

Features will be apparent to those of skill in the art by describing indetail exemplary embodiments with reference to the attached drawings inwhich:

FIG. 1 illustrates a plan view of a semiconductor memory deviceaccording to some embodiments.

FIG. 2 illustrates an enlarged view of a cell array region illustratedin FIG. 1.

FIGS. 3A to 11A illustrate cross-sectional views taken along a line A-A′of FIG. 2 to show stages in a method of manufacturing a semiconductormemory device, according to some embodiments.

FIGS. 3B to 11B illustrate cross-sectional views taken along lines B-B′and C-C′ of FIG. 1 to show stages in a method of manufacturing asemiconductor memory device, according to some embodiments.

FIGS. 3C to 11C illustrate cross-sectional views taken along lines D-D′and E-E′ of FIG. 1 to show stages in a method of manufacturing asemiconductor memory device, according to some embodiments.

FIG. 11D illustrates a cross-sectional view taken along a line F-F′ ofFIG. 2.

FIG. 12A illustrates an enlarged view of a region ‘Q’ of FIG. 11Aaccording to some embodiments.

FIG. 12B illustrates an enlarged view of a comparative examplecorresponding to the region ‘Q’ of FIG. 11A.

FIGS. 13A and 13B illustrate cross-sectional views taken along the linesA-A′ and F-F′ of FIG. 2 of a semiconductor memory device according tosome embodiments.

DETAILED DESCRIPTION

FIG. 1 illustrates a plan view of a semiconductor memory deviceaccording to some embodiments. FIG. 2 illustrates an enlarged view of acell array region CAR illustrated in FIG. 1. FIGS. 3A to 11A, 3B to 11B,and 3C to 11C illustrate cross-sectional views taken along a line A-A′of FIG. 2 and B-B′, C-C′, D-D′, and E-E′ of FIG. 1 to show stages in amethod of manufacturing a semiconductor memory device, according to someembodiments. FIG. 11D illustrates a cross-sectional view taken along aline F-F′ of FIG. 2.

Referring to FIGS. 1, 2, and 3A to 3C, a substrate 100 including a cellarray region CAR and a peripheral circuit region PCR may be provided.The cell array region CAR may be a region on which memory cells aredisposed. The peripheral circuit region PCR may be a region on which,e.g., a word line driver, a sense amplifier, row and column decoders,and control circuits are disposed. The peripheral circuit region PCR mayinclude an NMOSFET region NR and a PMOSFET region PR. The NMOSFET regionNR may include a first region PCR1 and a second region PCR2. The PMOSFETregion PR may include a third region PCR3 and a fourth region PCR4. Thefirst and third regions PCR1 and PCR3 may be regions on whichhigh-voltage transistors are formed. The second and fourth regions PCR2and PCR4 may be regions on which low-voltage transistors are formed.

Device isolation layers 101 may be formed in the substrate 100 to defineactive regions AR in the cell array region CAR. In an implementation,the substrate 100 may be a silicon substrate. The active regions AR mayhave bar shapes laterally separated from each other, and each of theactive regions AR may extend in a third direction (hereinafter, referredto as ‘a D3 direction’) non-perpendicular to a first direction(hereinafter, referred to as ‘a D1 direction’) and a second direction(hereinafter, referred to as ‘a D2 direction’). The D1 direction and theD2 direction may intersect each other and may be parallel to a topsurface of the substrate 100.

A dopant region (see 21 and 22 of FIGS. 2 and 11D) may be formed in anupper portion (e.g., one end or side) of each of the active regions AR.The dopant region may be formed by implanting dopant ions, which have adifferent conductivity type from the substrate 100, into an upperportion (e.g., one surface or side) of the substrate 100. In animplementation, a depth of the dopant region may be smaller than depthsof the device isolation layers 101 (e.g., from the one surface or sideof the substrate 100). The dopant region may be formed after or beforethe formation of the device isolation layers 101. In an implementation,the dopant region may be formed in a subsequent process rather than thepresent process. The dopant region may be confinedly formed in the cellarray region CAR, e.g., only in the cell array region CAR. For example,the peripheral circuit region PCR may be covered with a mask layer whenthe dopant region is formed, and the dopant region may not be formed inthe peripheral circuit region PCR.

Trenches 11 may be formed in an upper portion (e.g., the one surface orside) of the substrate 100 of the cell array region CAR. The trenches 11may extend in the D1 direction and may be spaced apart from each otherin the D2 direction, and the dopant region may be divided into first andsecond dopant regions 21 and 22 by the trenches 11. For example, thefirst dopant region 21 may be between a pair of the second dopantregions 22 in one active region AR, and the first dopant region 21 andthe second dopant regions 22 may be separated from each other by thetrenches 11 in the one active region AR.

In an implementation, a first mask pattern MP may be formed on the topsurface (e.g., the one surface or side) of the substrate 100, and thetrenches 11 may be formed by dry and/or wet etching process using thefirst mask pattern MP as an etch mask. The first mask pattern MP maycover the peripheral circuit region PCR, and the etching process may notbe performed on the peripheral circuit region PCR. In an implementation,the first mask pattern MP may include, e.g., at least one of a siliconoxide layer, a silicon nitride layer, or a silicon oxynitride layer.Depths of the trenches 11 may be smaller than the depths of the deviceisolation layers 101.

Cell gate insulating patterns 126, cell gate conductive patterns 121,and capping patterns 129 may be sequentially formed on the resultantstructure having the trenches 11. In an implementation, the cell gateconductive patterns 121 may be word lines WL. In an implementation, acell gate insulating layer and a cell gate conductive layer may beformed in the trenches 11, and then, the cell gate insulating layer andthe cell gate conductive layer may be etched to form the cell gateinsulating patterns 126 and the cell gate conductive patterns 121 inlower regions of the trenches 11. The capping patterns 129 may be formedon the cell gate conductive patterns 121. An insulating layer may fillresidual regions or remaining portions of the trenches 11 (e.g., inwhich the cell gate conductive patterns 121 have already formed), andthen, an etch-back process may be performed on the insulating layer toform the capping patterns 129 (e.g., filling an upper portion near anopening of the trench).

For example, the cell gate insulating patterns 126 may include at leastone of a silicon oxide layer, a silicon nitride layer, or a siliconoxynitride layer. The cell gate conductive patterns 121 may include atleast one of a doped semiconductor material, a conductive metal nitride,a metal, or a metal-semiconductor compound (e.g., a metal silicide). Thecapping pattern 129 may include at least one of a silicon nitride layer,a silicon oxide layer, or a silicon oxynitride layer. Each of the cellgate insulating patterns 126, the cell gate conductive patterns 121, andthe capping patterns 129 may be formed using at least one of a chemicalvapor deposition (CVD) process, a physical vapor deposition (PVD)process, or an atomic layer deposition (ALD) process.

Referring to FIGS. 1, 2, and 4A to 4C, the first mask pattern MP may beremoved. The first mask pattern MP may be removed by a wet etchingprocess. During the removal process of the first mask pattern MP, upperportions of the capping patterns 129 may also be etched to form recessregions RS on or overlying the cell gate conductive patterns 121. Therecess regions RS may extend in the D1 direction along the trenches 11and may be spaced apart from each other in the D2 direction. Depths ofthe recess regions RS may be about 10% to about 40% of the depth of thetrench 11.

Referring to FIGS. 1, 2, and 5A to 5C, a mask layer 130 may be formed tocover an entire region of the substrate 100, and then, a photoresistpattern 135 may be formed to cover the cell array region CAR. Thephotoresist pattern 135 may cover a portion of the peripheral circuitregion PCR. In an implementation, the photoresist pattern 135 may coverthe NMOSFET region NR (e.g., the first and second regions PCR1 and PCR2)of the peripheral circuit region PCR and may expose the PMOSFET regionPR (e.g., the third and fourth regions PCR3 and PCR4) of the peripheralcircuit region PCR. The mask layer 130 may fill the recess regions RS.In an implementation, the mask layer 130 may include a silicon oxidelayer. The mask layer 130 may completely fill the recess regions RS andmay extend onto the top or upper surface of the substrate 100 betweenthe recess regions RS.

Referring to FIGS. 1, 2, and 6A to 6C, the mask layer 130 may bepatterned using the photoresist pattern 135 as an etch mask to form asecond mask pattern 131. The second mask pattern 131 may cover the cellarray region CAR and the NMOSFET region NR and may expose the PMOSFETregion PR. During the patterning process, an upper portion of thePMOSFET region PR may also be etched and removed. As a result, a top orupper surface of the PMOSFET region PR may be lower than top or uppersurfaces of the cell array region CAR and the NMOSFET region NR. In animplementation, the upper portion of the PMOSFET region PR may not beremoved.

A semiconductor layer SP may be formed on the substrate 100 of theexposed PMOSFET region PR. The semiconductor layer SP may be formed by aselective epitaxial growth (SEG) process. The cell array region CAR andthe NMOSFET region PR may be covered by the second mask pattern 131, andthe semiconductor layer SP may not be formed thereon. The semiconductorlayer SP may include a semiconductor material of which a carriermobility is higher than that of silicon. For example, the semiconductorlayer SP may be a silicon-germanium layer of which a lattice constant isdifferent from that of the substrate 100. In an implementation, thesemiconductor layer SP may have a thickness of about 80 Å to about 120Å.

Referring to FIGS. 1, 2, and 7A to 7C, the second mask pattern 131 maybe removed from the cell array region CAR and the NMOSFET region NR.Portions of the second mask pattern 131 may remain in the recess regionsRS, and remaining patterns 132 may be formed in the recess regions RS. Abuffer pattern BP may be formed to cover the cell array region CAR andto expose the peripheral circuit region PCR. A bottom (e.g.,substrate-facing) surface of the buffer pattern BP may be in contactwith a top or upper surface of the remaining pattern 132. In animplementation, the buffer pattern BP may include a first buffer pattern137 and a second buffer pattern 138 on the first buffer pattern 137. Thefirst buffer pattern 137 and the second buffer pattern 138 may be formedof different materials. For example, the first buffer pattern 137 may bea silicon oxide layer, and the second buffer pattern 138 may be asilicon nitride layer. In an implementation, a silicon oxide layer and asilicon nitride layer may be sequentially formed on an entire surface ofthe substrate 100, and a patterning process may be performed on thesilicon nitride layer and the silicon oxide layer by using a photoresistpattern covering the cell array region CAR and exposing the peripheralcircuit region PCR, thereby forming the buffer pattern BP. In animplementation, an additional silicon oxide layer may be providedbetween the second buffer pattern 138 and the photoresist pattern.

Referring to FIGS. 1, 2, and 8A to 8C, a first gate insulating layer 31may be formed on the first and third regions PCR1 and PCR3 correspondingto the high-voltage transistor regions. Thereafter, a second gateinsulating layer 32 may be formed on an entire surface of the substrate100. In an implementation, before the formation of the second gateinsulating layer 32, a third gate insulating layer 30 may be formed onthe second and fourth regions PCR2 and PCR4 corresponding to thelow-voltage transistor regions. The first and second gate insulatinglayers 31 and 32 may also be formed on the cell array region CAR.

A dielectric constant of the first gate insulating layer 31 may be lowerthan dielectric constants of the second and third gate insulating layers32 and 30. In an implementation, the first gate insulating layer 31 mayinclude a silicon oxide layer and/or a silicon oxynitride layer. Thefirst gate insulating layer 31 may be thicker than the second and thirdgate insulating layers 30 and 32. The second gate insulating layer 32may be a high-k dielectric layer of which a dielectric constant ishigher than that of a silicon oxide layer. The dielectric constant ofthe second gate insulating layer 32 may be higher than the dielectricconstants of the first and third gate insulating layers 31 and 30. In animplementation, the second gate insulating layer 32 may include anoxide, nitride, silicide, oxynitride, or silicide-oxynitride thatincludes hafnium (Hf), aluminum (Al), zirconium (Zr), or lanthanum (La).Each of the first and second gate insulating layers 31 and 32 may beformed using an ALD process, a CVD process, or a PVD process. In animplementation, the third gate insulating layer 30 may include a siliconoxide layer or a silicon oxynitride layer. In an implementation, thethird gate insulating layer 30 may be formed by a thermal oxidationand/or thermal nitrification process consuming the exposed substrate 100or the exposed semiconductor layer SP.

Referring to FIGS. 1, 2, and 9A to 9C, a first work-function adjustmentlayer 33 may be formed on the NMOSFET region NR, and a secondwork-function adjustment layer 34 may be formed on the PMOSFET regionPR. The first and second gate insulating layers 31 and 32 on the cellarray region CAR may be removed. The first and second work-functionadjustment layers 33 and 34 may help implement a desired thresholdvoltage and other performances of each of transistors. Each of the firstand second work-function adjustment layers 33 and 34 may be asingle-layered or multi-layered metal containing layer having a specificwork-function.

In an implementation, the second work-function adjustment layer 34 mayinclude TiN, TiN/TaN, Al₂O₃/TiN, Al/TiN, TiN/Al/TiN, TiN/TiON, Ta/TiN,or TaN/TiN. In an implementation, TiN of these materials may be replacedwith TaN, TaCN, TiCN, CoN, or CoCN. The second work-function adjustmentlayer 34 may have a thickness of 30 Å to 60 Å. The first work-functionadjustment layer 33 may include the same layer as the secondwork-function adjustment layer 34 and may further include layersincluding La/TiN, Mg/TiN, or Sr/TiN disposed on the same layer. In animplementation, La may be replaced with LaO or LaON.

Referring to FIGS. 1, 2, and 10A to 10C, a first conductive layer 141may be formed on the cell array region CAR and the peripheral circuitregion PCR. The first conductive layer 141 may include a dopedsemiconductor layer. In an implementation, the first conductive layer141 may include a poly-silicon layer doped with P-type dopants. A firstcontact CT1 may be formed to penetrate the first conductive layer 141and the buffer pattern BP. The first contact CT1 may be connected to thefirst dopant region 21. The first contact CT1 may include at least oneof a doped semiconductor material, a conductive metal nitride, or ametal. After the formation of the first contact CT1, a barrier layer 142and a second conductive layer 143 may be sequentially formed on the cellarray region CAR and the peripheral circuit region PCR. The barrierlayer 142 may include at least one of a conductive metal nitride, ametal-silicon compound, or a metal-silicon nitride. The secondconductive layer 143 may include at least one of a metal, a conductivemetal nitride, or a metal-silicon compound. In an implementation, thesecond conductive layer 143 may include at least one of tungsten (W),titanium (Ti), or tantalum (Ta). Each of the first conductive layer 141,the barrier layer 142, and the second conductive layer 143 may be formedusing an ALD process or a PVD process.

Referring to FIGS. 1, 2, and 11A to 11D, a capping layer 151 may beformed, and then, a patterning process may be performed to formconductive lines on the cell array region CAR and to form first tofourth transistors TR1 to TR4 (e.g., gate patterns, including gateelectrodes, of the first to fourth transistors TR1 to TR4) on theperipheral circuit region PCR. In an implementation, the conductivelines may be bit lines BL. The first conductive layer 141, the barrierlayer 142, and the second conductive layer 143 may be formed into afirst conductive pattern 145, a barrier pattern 146, and a secondconductive pattern 147, respectively, by the patterning process. Thepatterning process may be performed using the buffer pattern BP as anetch stop layer. Thereafter, first source/drain regions 161 may beformed in the NMOSFET region NR, and second source/drain regions 162 maybe formed in the PMOSFET region PR. In an implementation, the firstsource/drain regions 161 may be N-type dopant regions, and the secondsource/drain regions 162 may be P-type dopant regions. Spacers 152 maybe formed on sidewalls of the bit lines BL and the first to fourthtransistors TR1 to TR4. In an implementation, the spacers 152 mayinclude silicon oxide.

Contact holes may be formed to expose the second dopant regions 22, andsecond contacts CT2 may fill the contact holes. The second contacts CT2may include at least one of a metal, a conductive metal nitride, or ametal-silicon compound. In an implementation, each of the secondcontacts CT2 may include a poly-silicon pattern and a metal pattern thatare sequentially stacked. Data storage structures or parts DS may beformed on the second contacts CT2. In an implementation, when thesemiconductor memory device of the inventive concepts is a dynamicrandom access memory (DRAM) device, the data storage part DS may be acapacitor including a lower electrode, a dielectric layer, and an upperelectrode. In an implementation, the data storage part DS may include aphase-change layer, a variable resistance layer, or a magnetic tunneljunction layer.

FIG. 12A illustrates an enlarged view of a region ‘Q’ of FIG. 11Aaccording to some embodiments, and FIG. 12B illustrates an enlarged viewof a comparative example corresponding to the region ‘Q’ of FIG. 11A.The region ‘Q’ may correspond to a boundary region of the cell arrayregion CAR and the peripheral circuit region PCR. End portions of thebit lines BL may be provided in the region ‘Q’. The comparative exampleof FIG. 12B illustrates a resultant structure in which the bufferpattern BP is formed before the formation of the semiconductor layer SP.A portion of the first mask pattern MP may not be completely removed, asshown in the comparative example of FIG. 12B. Thus, sidewalls of theremaining parts first mask pattern MP and the first buffer pattern 137disposed thereon may be excessively recessed in the patterning processdescribed with reference to FIGS. 11A to 11D, and thus an undercutregion UC may be formed. Therefore, a conductive residue MS may occur orresult in an interlayer insulating layer 157 covering the undercutregion UC. The conductive residue MS may occur by or during a depositionprocess of a conductive material for forming a contact or electrodeformed after the formation of the undercut region UC. For example, theconductive residue MS may include a metal material such as La, Ti, Al,or Hf. The conductive residue MS may extend along a boundary of the cellarray region CAR and the peripheral circuit region PCR, and thus anelectrical short could be caused between interconnection lines of asemiconductor memory device.

Referring to FIG. 12A, according to some embodiments, the buffer patternBP may be formed after the formation of the semiconductor layer SP.Thus, an undercut region and a conductive residue may not be present, asillustrated in FIG. 12A. To completely remove the remaining first maskpattern MP, the etching process may be performed until the recessregions RS are formed, as described with reference to FIGS. 4A to 4C. Ifthe buffer pattern BP were to be formed before the formation of thesemiconductor layer SP, like the comparative example, the recess regionsRS may not be completely filled due to the buffer pattern BP having arelatively thin thickness. In an implementation, the semiconductor layerSP may be formed after the formation of the recess regions RS and beforethe formation of the buffer pattern BP. The recess regions RS may befilled with the portions of the second mask pattern 131 for forming thesemiconductor layer SP, and the electrical short between interconnectionlines of a semiconductor memory device of FIG. 12B may be avoided. Thus,reliability of the semiconductor memory device may be improved.

The semiconductor memory device according to some embodiments mayinclude word line structures in the trenches 11 formed in the upperportion of the substrate 100, and each of the word line structures mayinclude the word line WL, the capping pattern 129 and the remainingpattern 132, which are sequentially stacked in each of the trenches 11.The remaining pattern 132 may extend along the top surface of the wordline WL. The word line structures may intersect the active regions AR todivide the active regions AR into the first dopant regions 21 and thesecond dopant regions 22. The bit lines BL may extend in the D2direction and may be connected to the first dopant regions 21 throughthe first contacts CT1. The second dopant regions 22 may be connected tothe data storage parts DS through the second contacts CT2. The bufferpattern BP may be provided between the substrate 100 and the bit linesBL, and the first contacts CT1 and the second contacts CT2 may penetratethe buffer pattern BP. The first contacts CT1 may penetrate the bufferpattern BP so as to be connected to the remaining pattern 132.

The semiconductor memory device according to some embodiments mayinclude the first transistor TR1 and the second transistor TR2 on theNMOSFET region NR and may include the third transistor TR3 and thefourth transistor TR4 on the PMOSFET region PR. The third and fourthtransistors TR3 and TR4 may use the semiconductor layer SP including thesemiconductor material (e.g., silicon-germanium) having a high carriermobility as channel regions. Each of the first and third transistors TR1and TR3 corresponding to the high-voltage transistors may include thefirst gate insulating layer 31 and the second gate insulating layer 32,and each of the second and fourth transistors TR2 and TR4 correspondingto the low-voltage transistors may include the third gate insulatinglayer 30 and the second gate insulating layer 32. Each of the first andsecond transistors TR1 and TR2 may include the first work-functionadjustment layer 33, and each of the third and fourth transistors TR3and TR4 may include the second work-function adjustment layer 34. Eachof the first to fourth transistors TR1 to TR4 may include the firstconductive pattern 145, the barrier pattern 146, the second conductivepattern 147, and the capping layer 151.

FIGS. 13A and 13B illustrate cross-sectional views taken along the linesA-A′ and F-F′ of FIG. 2 to show a semiconductor memory device accordingto some embodiments. Hereinafter, repeated descriptions to the sameelements as in the above embodiments may be omitted for the purpose ofease and convenience in explanation.

Referring to FIGS. 13A and 13B, a buffer pattern BP may be a singlelayer of the first buffer pattern 137 without the second buffer pattern138. For example, the first buffer patterns 137 may be a silicon oxidelayer.

As is traditional in the field, embodiments are described, andillustrated in the drawings, in terms of functional blocks, units and/ormodules. Those skilled in the art will appreciate that these blocks,units and/or modules are physically implemented by electronic (oroptical) circuits such as logic circuits, discrete components,microprocessors, hard-wired circuits, memory elements, wiringconnections, and the like, which may be formed using semiconductor-basedfabrication techniques or other manufacturing technologies. In the caseof the blocks, units and/or modules being implemented by microprocessorsor similar, they may be programmed using software (e.g., microcode) toperform various functions discussed herein and may optionally be drivenby firmware and/or software. Alternatively, each block, unit and/ormodule may be implemented by dedicated hardware, or as a combination ofdedicated hardware to perform some functions and a processor (e.g., oneor more programmed microprocessors and associated circuitry) to performother functions. Also, each block, unit and/or module of the embodimentsmay be physically separated into two or more interacting and discreteblocks, units and/or modules without departing from the scope herein.Further, the blocks, units and/or modules of the embodiments may bephysically combined into more complex blocks, units and/or moduleswithout departing from the scope herein.

By way of summation and review, new exposure techniques and/or expensiveexposure techniques may be needed to form fine patterns, and it may bedifficult to highly integrate semiconductor devices. Thus, newintegration techniques are being considered.

According to some embodiments, it is possible to help prevent theconductive residue from being formed between the cell array region andthe peripheral circuit region. Thus, the reliability of thesemiconductor memory device may be improved.

The embodiments may provide a semiconductor memory device with improvedreliability.

Example embodiments have been disclosed herein, and although specificterms are employed, they are used and are to be interpreted in a genericand descriptive sense only and not for purpose of limitation. In someinstances, as would be apparent to one of ordinary skill in the art asof the filing of the present application, features, characteristics,and/or elements described in connection with a particular embodiment maybe used singly or in combination with features, characteristics, and/orelements described in connection with other embodiments unless otherwisespecifically indicated. Accordingly, it will be understood by those ofskill in the art that various changes in form and details may be madewithout departing from the spirit and scope of the present invention asset forth in the following claims.

1.-24. (canceled)
 25. A semiconductor memory device, comprising: asubstrate that includes active regions defined by a device isolationlayer; word line structures filling trenches formed in an upper portionof the substrate, the word line structures intersecting the activeregions to divide the active regions into first dopant regions andsecond dopant regions; bit lines intersecting the word line structures,the bit lines being connected to the first dopant regions; and datastorage parts connected to the second dopant regions, wherein each ofthe word line structures includes a word line, a capping pattern, and aremaining pattern, which are sequentially stacked in each of thetrenches.
 26. The semiconductor memory device as claimed in claim 25,wherein the remaining pattern extends along a top surface of the wordline.
 27. The semiconductor memory device as claimed in claim 25,further comprising a buffer pattern between the substrate and the bitlines, wherein a top surface of the remaining pattern is in contact witha bottom surface of the buffer pattern.
 28. The semiconductor memorydevice as claimed in claim 27, further comprising first contactsconnecting the bit lines to the first dopant regions, wherein the firstcontacts penetrate the buffer pattern so as to be connected to theremaining pattern.
 29. The semiconductor memory device as claimed inclaim 28, wherein each of bottom surfaces of the first contacts ishigher than a top surface of the capping pattern.
 30. The semiconductormemory device as claimed in claim 28, wherein each of bottom surfaces ofthe first contacts is lower than a bottom surface of the remainingpattern.
 31. The semiconductor memory device as claimed in claim 27,further comprising an interlayer insulating layer covering side surfacesof the bit lines, wherein the interlayer insulating layer penetrates thebuffer pattern so as to be connected to the device isolation layer. 32.The semiconductor memory device as claimed in claim 27, wherein thebuffer pattern comprises a first buffer pattern and a second bufferpattern, the first buffer pattern and the second buffer pattern areformed of different materials.
 33. The semiconductor memory device asclaimed in claim 25, wherein the remaining pattern comprises a stepwisestructure including a side surface and a bottom surface.
 34. Thesemiconductor memory device as claimed in claim 33, further comprising afirst contact connecting each of the bit lines to the first dopantregions, wherein the bottom surface of the stepwise structure contacts abottom surface of the first contact.
 35. The semiconductor memory deviceas claimed in claim 25, wherein a width of the remaining patterndecreases from a top surface of the remaining pattern to a bottomsurface of the remaining pattern.
 36. The semiconductor memory device asclaimed in claim 25, wherein a side surface of the remaining patternaligns with a side surface of the capping pattern.
 37. The semiconductormemory device as claimed in claim 25, wherein a bottom surface of theremaining pattern is higher than bottom surfaces of the first dopantregions.
 38. A semiconductor memory device, comprising: a substrate thatincludes active regions defined by a device isolation layer; a word linestructure filling a trench formed in an upper portion of the substrate,the word line structure intersecting the active regions to divide theactive regions into a first dopant region and a second dopant region; abit line intersecting the word line structure, the bit line beingconnected to the first dopant region; a buffer pattern between thesubstrate and the bit lines; and a first contact connecting the bit lineto the first dopant region, wherein the word line structure includes aword line, a capping pattern, and a remaining pattern, which aresequentially stacked in the trench, and the first contacts penetrate thebuffer pattern so as to be connected to the remaining pattern.
 39. Thesemiconductor memory device as claimed in claim 38, wherein a bottomsurface of the first contact is higher than a top surface of the cappingpattern.
 40. The semiconductor memory device as claimed in claim 38,wherein the remaining pattern comprises a stepwise structure including aside surface and a bottom surface, the bottom surface of the stepwisestructure contacts a bottom surface of the first contact.
 41. Thesemiconductor memory device as claimed in claim 38, wherein theremaining pattern extends along a top surface of the word line.
 42. Asemiconductor memory device, comprising: a substrate that includesactive regions defined by a device isolation layer; word line structuresfilling trenches formed in an upper portion of the substrate, the wordline structures intersecting the active regions to divide the activeregions into first dopant regions and second dopant regions; bit linesintersecting the word line structures, the bit lines being connected tothe first dopant regions; a first contact connecting the bit line to thefirst dopant region; and data storage parts connected to the seconddopant regions, wherein each of the word line structures includes a wordline, a capping pattern, and a remaining pattern, which are sequentiallystacked in each of the trenches, and the remaining pattern comprises astepwise structure connected to a bottom portion of the first contact.43. The semiconductor memory device as claimed in claim 42, wherein theremaining pattern extends along a top surface of the word line.
 44. Thesemiconductor memory device as claimed in claim 42, wherein a bottomsurface of the first contact is higher than a top surface of the cappingpattern.